Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Numerical recipes in C: the art of scientific computing
Numerical recipes in C: the art of scientific computing
A portable global optimizer and linker
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Numerical recipes in C (2nd ed.): the art of scientific computing
Numerical recipes in C (2nd ed.): the art of scientific computing
Avoiding conditional branches by code replication
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Accurate static branch prediction by value range propagation
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Static cache simulation and its applications
Static cache simulation and its applications
Interprocedural conditional branch elimination
Proceedings of the ACM SIGPLAN 1997 conference on Programming language design and implementation
Bounding Pipeline and Instruction Cache Performance
IEEE Transactions on Computers
Timing constraint specification and analysis
Software—Practice & Experience
Supporting Timing Analysis by Automatic Bounding of LoopIterations
Real-Time Systems - Special issue on worst-case execution-time analysis
Deriving Annotations for Tight Calculation of Execution Time
Euro-Par '97 Proceedings of the Third International Euro-Par Conference on Parallel Processing
Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques
LCTES '98 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Supporting the specification and analysis of timing constraints
RTAS '96 Proceedings of the 2nd IEEE Real-Time Technology and Applications Symposium (RTAS '96)
Bounding Loop Iterations for Timing Analysis
RTAS '98 Proceedings of the Fourth IEEE Real-Time Technology and Applications Symposium
Tighter Timing Predictions by Automatic Detection and Exploitation of Value-Dependent Constraints
RTAS '99 Proceedings of the Fifth IEEE Real-Time Technology and Applications Symposium
Worst case timing analysis of RISC processors: R3000/R3010 case study
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Efficient microarchitecture modeling and path analysis for real-time software
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Integrating the timing analysis of pipelining and instruction caching
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Deadline Analysis of Interrupt-Driven Software
IEEE Transactions on Software Engineering
Improving WCET by applying a WC code-positioning optimization
ACM Transactions on Architecture and Code Optimization (TACO)
Efficient detection and exploitation of infeasible paths for software timing analysis
Proceedings of the 43rd annual Design Automation Conference
Improving WCET by applying worst-case path optimizations
Real-Time Systems
Generalizing parametric timing analysis
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Chronos: A timing analyzer for embedded software
Science of Computer Programming
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Symbolic simulation on complicated loops for WCET path analysis
EMSOFT '11 Proceedings of the ninth ACM international conference on Embedded software
Trace acquirement from real-time systems based on WCET analysis
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Analyzing loop paths for execution time estimation
ICDCIT'05 Proceedings of the Second international conference on Distributed Computing and Internet Technology
Computation takes time, but how much?
Communications of the ACM
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Predicting the worst-case execution time (WCET) and best-case execution time (BCET) of a real-time program is a challenging task. Though much progress has been made in obtaining tighter timing predictions by using techniques that model the architectural features of a machine, significant overestimations of WCET and underestimations of BCET can still occur. Even with perfect architectural modeling, dependencies on data values can constrain the outcome of conditional branches and the corresponding set of paths that can be taken in a program. While branch constraint information has been used in the past by some timing analyzers, it has typically been specified manually, which is both tedious and error prone. This paper describes efficient techniques for automatically detecting branch constraints by a compiler and automatically exploiting these constraints within a timing analyzer. The result is significantly tighter timing analysis predictions without requiring additional interaction with a user.