Evaluating Associativity in CPU Caches
IEEE Transactions on Computers
Performance analysis of embedded software using implicit path enumeration
LCTES '95 Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems
Timing Analysis for Instruction Caches
Real-Time Systems - Special issue on worst-case execution-time analysis
Efficient longest executable path search for programs with complex flows and pipeline effects
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Cache Behavior Prediction by Abstract Interpretation
SAS '96 Proceedings of the Third International Symposium on Static Analysis
Integrating the timing analysis of pipelining and instruction caching
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Exploiting stack distance to estimate worst-case data cache performance
Proceedings of the 2009 ACM symposium on Applied Computing
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The worst-case execution time (WCET) analysis is critical to ensure the schedulability and correctness of hard real-time systems. Modern microprocessors, however, make the WCET analysis complicated, mainly because of their performance acceleration features like caches, pipelines, out-of-order execution, etc. This paper focuses on studying an accurate static timing analysis approach for instruction caches with the LRU-based strategy by computing the worst-case stack distance. The experimental results indicate that our approach can accurately predict worst-case instruction cache performance. Also, the stack distance based timing analysis approach can efficiently categorize worst-case instruction cache misses into cold, conflict and capacity misses, which can provide useful insights to improve the worst-case instruction cache performance.