Probabilistic timing analysis on conventional cache designs

Authors:
Leonidas Kosmidis;Charlie Curtsinger;Eduardo Quiñones;Jaume Abella;Emery Berger;Francisco J. Cazorla
Affiliations:
Barcelona Supercomputing Center (BSC). Barcelona, Spain and Universitat Politècnica de Catalunya (UPC), Barcelona, Spain;University of Massachusetts (UMass), Amherst, MA;Barcelona Supercomputing Center (BSC), Barcelona, Spain;Barcelona Supercomputing Center (BSC), Barcelona, Spain;University of Massachusetts (UMass), Amherst, MA;Spanish National Research Council (IIIA-CSIC), Barcelona, Spain and Barcelona Supercomputing Center (BSC), Barcelona, Spain
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2013

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Abstract

Probabilistic timing analysis (PTA), a promising alternative to traditional worst-case execution time (WCET) analyses, enables pairing time bounds (named probabilistic WCET or pWCET) with an exceedance probability (e.g., 10-16), resulting in far tighter bounds than conventional analyses. However, the applicability of PTA has been limited because of its dependence on relatively exotic hardware: fully-associative caches using random replacement. This paper extends the applicability of PTA to conventional cache designs via a software-only approach. We show that, by using a combination of compiler techniques and runtime system support to randomise the memory layout of both code and data, conventional caches behave as fully-associative ones with random replacement.