A Case for Direct-Mapped Caches
Computer
Evaluating Associativity in CPU Caches
IEEE Transactions on Computers
Stack-based scheduling for realtime processes
Real-Time Systems
An extendible approach for analyzing fixed priority hard real-time tasks
Real-Time Systems
Compiler support for software-based cache partitioning
LCTES '95 Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems
CPU Cache Prefetching: Timing Evaluation of Hardware Implementations
IEEE Transactions on Computers
Analysis of Cache-Related Preemption Delay in Fixed-Priority Preemptive Scheduling
IEEE Transactions on Computers
Adding instruction cache effect to schedulability analysis of preemptive real-time systems
RTAS '96 Proceedings of the 2nd IEEE Real-Time Technology and Applications Symposium (RTAS '96)
Measuring the Performance of Schedulability Tests
Real-Time Systems
Scheduling Analysis of Real-Time Systems with Precise Modeling of Cache Related Preemption Delay
ECRTS '05 Proceedings of the 17th Euromicro Conference on Real-Time Systems
Experiments with WCET-Oriented Programming and the Single-Path Architecture
WORDS '05 Proceedings of the 10th IEEE International Workshop on Object-Oriented Real-Time Dependable Systems
Computer Architecture, Fourth Edition: A Quantitative Approach
Computer Architecture, Fourth Edition: A Quantitative Approach
Timing analysis for preemptive multitasking real-time systems with caches
ACM Transactions on Embedded Computing Systems (TECS)
Compile-time decided instruction cache locking using worst-case execution paths
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Data cache locking for tight timing calculations
ACM Transactions on Embedded Computing Systems (TECS)
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Efficient Exact Schedulability Tests for Fixed Priority Real-Time Systems
IEEE Transactions on Computers
Real-Time Systems and Programming Languages: Ada, Real-Time Java and C/Real-Time POSIX
Real-Time Systems and Programming Languages: Ada, Real-Time Java and C/Real-Time POSIX
Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cache-related preemption delay via useful cache blocks: Survey and redefinition
Journal of Systems Architecture: the EUROMICRO Journal
CAMA: A Predictable Cache-Aware Memory Allocator
ECRTS '11 Proceedings of the 2011 23rd Euromicro Conference on Real-Time Systems
Cache Related Pre-emption Delay Aware Response Time Analysis for Fixed Priority Pre-emptive Systems
RTSS '11 Proceedings of the 2011 IEEE 32nd Real-Time Systems Symposium
Instruction cache locking for multi-task real-time embedded systems
Real-Time Systems
Explicit Reservation of Local Memory in a Predictable, Preemptive Multitasking Real-Time System
RTAS '12 Proceedings of the 2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium
Optimising task layout to increase schedulability via reduced cache related pre-emption delays
Proceedings of the 20th International Conference on Real-Time and Network Systems
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We describe and evaluate explicit reservation of cache memory to reduce the cache-related preemption delay (CRPD) observed when tasks share a cache in a preemptive multitasking hard real-time system. We demonstrate the approach using measurements obtained from a hardware prototype, and present schedulability analyses for systems that share a cache by explicit reservation. These analyses form the basis for a series of experiments to further evaluate the approach. We find that explicit reservation is most useful for larger task sets with high utilization. Some task sets cannot be scheduled with a conventional cache, but are schedulable with explicit reservation.