Tradeoffs in supporting two page sizes
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
On the instruction-level characteristics of scalar code in highly-vectorized scientific applications
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
A fill-unit approach to multiple instruction issue
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
POWER2 floating-point unit: architecture and implementation
IBM Journal of Research and Development
Design at the system level with VLSI CMOS
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Reducing TLB and memory overhead using online superpage promotion
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Optimization of machine descriptions for efficient use
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Two-ported cache alternatives for superscalar processors
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
Optimization of Machine Descriptions for Efficient Use
International Journal of Parallel Programming
IEEE Micro
UltraSPARC: Compiling for Maximum Floating Point Performance
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
Instruction code mapping for performance increase and energy reduction in embedded computer systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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