Predicting performance potential of modern DSPs

Authors:
Naji Ghazal;Richard Newton;Jan Rabaey
Affiliations:
Department of EECS, University of California, Berkeley, CA;Department of EECS, University of California, Berkeley, CA;Department of EECS, University of California, Berkeley, CA
Venue:
Proceedings of the 37th Annual Design Automation Conference
Year:
2000

Citing 9
Cited 3

Performance evaluation for application-specific architectures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Compiled Simulation of Programmable DSP Architectures

Journal of VLSI Signal Processing Systems - Special issue on the 1995 VLSI signal processing workshop
ISDL: an instruction set description language for retargetability

DAC '97 Proceedings of the 34th annual Design Automation Conference
Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator

DAC '98 Proceedings of the 35th annual Design Automation Conference
Retargetable estimation scheme for DSP architecture selection

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
DSP Processors Hit the Mainstream

Computer
MMX Technology Extension to the Intel Architecture

IEEE Micro
Describing instruction set processors using nML

EDTC '95 Proceedings of the 1995 European conference on Design and Test
Code optimization libraries for retargetable compilation for embedded digital signal processors

Code optimization libraries for retargetable compilation for embedded digital signal processors

Compiler-directed customization of ASIP cores

Proceedings of the tenth international symposium on Hardware/software codesign
Floating-to-fixed-point conversion for digital signal processors

EURASIP Journal on Applied Signal Processing
Compiler optimizations with DSP-Specific semantic descriptions

LCPC'02 Proceedings of the 15th international conference on Languages and Compilers for Parallel Computing

Quantified Score

Hi-index	0.01

Visualization

Abstract

High-level development tools for digital signal processors (DSPs) remain unable to extract optimal performance from them without the designer's in-depth knowledge of the architecture. In this paper we describe our approach to Retargetable Estimation and show how and why it can be effective in quickly predicting and guiding toward hand-optimized performance of moderns DSPs for a given application described in a high-level language. We also contrast the advantages of this scheme with those of a full-featured optimizing compiler.