Communications of the ACM
A hardware-software co-simulator for embedded system design and debugging
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
A Hardware-Software Codesign Methodology for DSP Applications
IEEE Design & Test
Insulin: An Instruction Set Simulation Environment
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
Predicting performance potential of modern DSPs
Proceedings of the 37th Annual Design Automation Conference
An ultra-fast instruction set simulator
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automated energy/performance macromodeling of embedded software
Proceedings of the 41st annual Design Automation Conference
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This paper presents a technique for simulating processors based onthe principle of compiled simulation. Unlike existing, commerciallyavailable instruction set simulators for DSPs, which are ofinterpretive character, the proposed technique performs instructiondecoding and simulation scheduling at compile time. The techniqueoffers up to three orders of magnitude faster simulation. The highspeed allows the user to explore algorithms and hardware/softwaretrade-offs before any hardware implementation. Moreover, the user cantailor the compiled simulation to trade speed for more accuracy. Inthis paper, the sources of the speedup and the limitations of thetechnique are analyzed and the realization of the simulation compileris presented.