Graph matching-based algorithms for FPGA segmentation design
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Graph matching-based algorithms for array-based FPGA segmentation design and routing
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
TORCH: a design tool for routing channel segmentation in FPGAs
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Exploring FPGA routing architecture stochastically
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
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The channel segmentation design problem for symmetrical FPGAs is the problem of designing segmented tracks in the interconnection channels that provides good net routability and delay performance at the same time. In this paper, we show how to separate the problem into the segmentation design problems of the vertical and horizontal channels by a statistical analysis of the net distribution on a symmetrical FPGA. And we propose an effective approach for segmented channel design when the allowed number of tracks in a channel is fixed and limited.