A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme

Authors:
Shusuke Yoshimoto;Masaharu Terada;Youhei Umeki;Shunsuke Okumura;Atsushi Kawasumi;Toshikazu Suzuki;Shinichi Moriwaki;Shinji Miyano;Hiroshi Kawaguchi;Masahiko Yoshimoto
Affiliations:
Kobe University, Kobe, Japan;Kobe University, Kobe, Japan;Kobe University, Kobe, Japan;Kobe University, Kobe, Japan;Semiconductor Technology Academic Research Center, Yokohama, Japan;Semiconductor Technology Academic Research Center, Yokohama, Japan;Semiconductor Technology Academic Research Center, Yokohama, Japan;Semiconductor Technology Academic Research Center, Yokohama, Japan;Kobe University, Kobe, Japan;Kobe University, Kobe, Japan
Venue:
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Year:
2012

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Abstract

This paper presents a novel read-bitline amplitude limiting (RBAL) scheme which suppresses dynamic energy dissipation caused by random variation. In addition, a discharge acceleration (DA) circuit is proposed to decrease delay overhead of RBAL. The proposed scheme improves the active energy dissipation in a read cycle by 22% at the center-center (CC) corner and 25°C. The maximum delay overhead is 32% at the fast-slow (FS) corner and -40°C. The circuits have been implemented using the 40-nm bulk CMOS process. The implemented 256-Kb 8T SRAM works fine with energy dissipation of sub-10 pJ / access from 0.5-0.7 V.