The impact of random device variation on SRAM cell stability in sub-90-nm CMOS technologies

Authors:
Kanak Agarwal;Sani Nassif
Affiliations:
IBM Corporation, Austin Research Laboratory, Austin, TX;IBM Corporation, Austin Research Laboratory, Austin, TX
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2008

Citing 6
Cited 8

Intrinsic MOSFET parameter fluctuations due to random dopant placement

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance

Proceedings of the 37th Annual Design Automation Conference
Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Variability in sub-100nm SRAM designs

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical analysis of SRAM cell stability

Proceedings of the 43rd annual Design Automation Conference
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Variation tolerant 9T SRAM cell design

Proceedings of the 20th symposium on Great lakes symposium on VLSI
Criterion to evaluate input-offset voltage of a latch-type sense amplifier

IEEE Transactions on Circuits and Systems Part I: Regular Papers
Leakage-aware redundancy for reliable sub-threshold memories

Proceedings of the 48th Design Automation Conference
Feedback control based cache reliability enhancement for emerging multicores

Proceedings of the International Conference on Computer-Aided Design
Sequential importance sampling for low-probability and high-dimensional SRAM yield analysis

Proceedings of the International Conference on Computer-Aided Design
Work-function variation induced fluctuation in bias-temperature-instability characteristics of emerging metal-gate devices and implications for digital design

Proceedings of the International Conference on Computer-Aided Design
Efficient importance sampling for high-sigma yield analysis with adaptive online surrogate modeling

Proceedings of the Conference on Design, Automation and Test in Europe

Quantified Score

Hi-index	0.00

Visualization

Abstract

The impact of process variation on SRAM yield has become a serious concern in scaled technologies. In this paper, we propose a methodology to analyze the stability of an SRAM cell in the presence of random fluctuations in the device parameters. First, we develop a theoretical framework for characterizing the dc noise margin of a memory cell. The framework is based on the concept that an SRAM cell is on the verge of instability when the gain across the loop formed by the cross-coupled inverters in the cell is unity. The noise margin criteria developed in this manner can be used to verify a cell stability in the presence of arbitrary DC noise offsets at the two storage nodes in the cell. We also develop metrics for estimating the cell stability during read and write operations and verify these models by extensive Monte Carlo simulations in a 65-nm CMOS process. Our results show that the proposed robustness metrics can be used to estimate cell failure probabilities in an efficient and accurate manner.