Control Techniques to Eliminate Voltage Emergencies in High Performance Processors
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Feedback Control of Computing Systems
Feedback Control of Computing Systems
The Soft Error Problem: An Architectural Perspective
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Mitigating soft error failures for multimedia applications by selective data protection
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
SPEC CPU2006 benchmark descriptions
ACM SIGARCH Computer Architecture News
Industry perspective on chip multi-threading, bridging the gap with academia using OpenSPARC
WCAE '07 Proceedings of the 2007 workshop on Computer architecture education
Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
The impact of random device variation on SRAM cell stability in sub-90-nm CMOS technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SHARP control: controlled shared cache management in chip multiprocessors
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Soft errors issues in low-power caches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Self-Adaptive Data Caches for Soft-Error Reliability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Focusing on data reliability, we propose a control theory centric approach designed to improve transient error resilience in shared caches of emerging multicores while satisfying performance goals. The proposed scheme takes, as input, two quality of service (QoS) specifications: performance QoS and reliability QoS. The first of these indicates the minimum workload-wide cache (L2) hit rate value acceptable, whereas the second one captures the reliability bound on an application basis, with the help of a metric called the Reads-with-Replica (RwR). We present an extensive experimental evaluation of the proposed scheme on various workloads formed using the applications from the SPEC2006 benchmark suite. The proposed scheme is able to satisfy, in most of the tested cases, both performance and reliability QoS targets, by successfully modulating the total size of the data replication area and partitioning of this area among the co-runner applications. The collected results also show that our scheme achieves consistent improvements under different values of the major simulation parameters.