Feedback control based cache reliability enhancement for emerging multicores
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
Chip Multi-Threading is the new wave that is sweeping this decade. It is no more a theoretical discussion topic but one where revolutionary products with CMT will permeate every aspect of computing infrastructure. So, how does Academia innovate on this new frontier? Sun Microsystems has contributed to the open-source community a large state-of-the-art design called the, OpenSPARC T1. This new open source version of the UltraSPARC T1 design is a 64 bit, 32 threaded processor design available at no charge. For the first time in history, developers gain access to the chip multi-threading (CMT) technology unique to the UltraSPARC T1 processor, which is released under the GNU General Public License (GPL). The specifications, verilog RTL, verification environment, diagnostic test suite, SPARC Architecture Model, instruction accurate simulator, OBP, hypervisor and Solaris OS image are all made available. In this presentation we will discuss what Sun Microsystems is doing to bring a commercial CMT architecture and design into the classroom, "Bridging the gap" between industry and academia.