Variation tolerant 9T SRAM cell design
Proceedings of the 20th symposium on Great lakes symposium on VLSI
| Hi-index | 0.00 |
A nine transistor (9T) cell at a 32nm feature size in CMOS is proposed to accomplish improvements in stability as well as power dissipation compared with previous designs for low-power memory operation. Initially, this paper shows that the proposed 9T SRAM cell can be used for robust, high-density design. Then, an optimum sizing is found for this 9T cell by considering stability, energy consumption, and performance. A write bitline balancing scheme is proposed to further reduce the power consumption of the SRAM cell. The impact of process variations is investigated in detail, and the power reduction of the 9T SRAM cell is verified under parameter variations.