Design and analysis of a 32nm PVT tolerant CMOS SRAM cell for low leakage and high stability
Integration, the VLSI Journal
IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM
Integration, the VLSI Journal
Impact of soft errors in a jet engine controller
SAFECOMP'12 Proceedings of the 31st international conference on Computer Safety, Reliability, and Security
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Nanometric SRAMs are more vulnerable to experiencing particle induced soft error due to lower operating voltages coupled with higher packing density and increased process variations. In this paper, we present a compact model for critical charge of a 6T SRAM cell for estimating the effects of process variations on its soft error susceptibility. The model is based on dynamic behavior of the cell and a simple decoupling technique for the non-linearly coupled storage nodes. The model describes the critical charge in terms of transistor parameters, cell supply voltage, and injected current parameters. Consequently, it enables investigating the spread of critical charge due to process induced variations in these parameters and to manufacturing defects, such as, resistive contacts or vias. In addition, the model can estimate the improvement in critical charge when MIM capacitors are added to the cell in order to improve the soft error robustness. The critical charge calculated by the model is in good agreement with SPICE simulations for a commercial 90nm CMOS process with a maximum discrepancy of less than 5%.