Single ended 6T SRAM with isolated read-port for low-power embedded systems

Authors:
Jawar Singh;Dhiraj K. Pradhan;Simon Hollis;Saraju P. Mohanty;J. Mathew
Affiliations:
University of Bristol, UK;University of Bristol, UK;University of Bristol, UK;University of North Texas;University of Bristol, UK
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2009

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Abstract

This paper presents a six-transistor (6T) single-ended static random access memory (SE-SRAM) bitcell with an isolated read-port, suitable for low-Vdd and low-power embedded applications. The proposed bitcell has a better static noise margin (SNM) and write-ability compared to a standard 6T bitcell and equivalent to an 8T bitcell [1]. An 8Kbit SRAM module with the proposed and standard 6T bitcells is simulated, including full blown parasitics using BPTM, 65nm CMOS technology node to evaluate and compare different performance parameters. The active power dissipation in the proposed 6T design is 28% and 25% less, compared to standard 6T and 8T SRAM modules respectively.