Dynamically reconfigurable hybrid cache: an energy-efficient last-level cache design

Authors:
Yu-Ting Chen;Jason Cong;Hui Huang;Bin Liu;Chunyue Liu;Miodrag Potkonjak;Glenn Reinman
Affiliations:
University of California, Los Angeles, CA;University of California, Los Angeles, CA;University of California, Los Angeles, CA;University of California, Los Angeles, CA;University of California, Los Angeles, CA;University of California, Los Angeles, CA;University of California, Los Angeles, CA
Venue:
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2012

Citing 19
Cited 3

Selective cache ways: on-demand cache resource allocation

Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Application-specific memory management for embedded systems using software-controlled caches

Proceedings of the 37th Annual Design Automation Conference
Reconfigurable caches and their application to media processing

Proceedings of the 27th annual international symposium on Computer architecture
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories

ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Cache decay: exploiting generational behavior to reduce cache leakage power

ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Fine-grain CAM-tag cache resizing using miss tags

Proceedings of the 2002 international symposium on Low power electronics and design
Simics: A Full System Simulation Platform

Computer
Adaptive mode control: A static-power-efficient cache design

ACM Transactions on Embedded Computing Systems (TECS)
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset

ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Challenges in sleep transistor design and implementation in low-power designs

Proceedings of the 43rd annual Design Automation Conference
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement

Proceedings of the 45th annual Design Automation Conference
The PARSEC benchmark suite: characterization and architectural implications

Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Architecting phase change memory as a scalable dram alternative

Proceedings of the 36th annual international symposium on Computer architecture
Hybrid cache architecture with disparate memory technologies

Proceedings of the 36th annual international symposium on Computer architecture
Morphable memory system: a robust architecture for exploiting multi-level phase change memories

Proceedings of the 37th annual international symposium on Computer architecture
An energy efficient cache design using spin torque transfer (STT) RAM

Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
An energy-efficient adaptive hybrid cache

Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Processor caches with multi-level spin-transfer torque ram cells

Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement

Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design

Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores

Proceedings of the Conference on Design, Automation and Test in Europe
Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Thread-criticality aware dynamic cache reconfiguration in multi-core system

Proceedings of the International Conference on Computer-Aided Design

Quantified Score

Hi-index	0.00

Visualization

Abstract

The recent development of non-volatile memory (NVM), such as spin-torque transfer magnetoresistive RAM (STT-RAM) and phase-change RAM (PRAM), with the advantage of low leakage and high density, provides an energy-efficient alternative to traditional SRAM in cache systems. We propose a novel reconfigurable hybrid cache architecture (RHC), in which NVM is incorporated in the last-level cache together with SRAM. RHC can be reconfigured by powering on/off SRAM/NVM arrays in a way-based manner. In this work, we discuss both the architecture and circuit design issues for RHC. Furthermore, we provide hardware-based mechanisms to dynamically reconfigure RHC on-the-fly based on the cache demand. Experimental results on a wide range of benchmarks show that the proposed RHC achieves an average 63%, 48% and 25% energy saving over non-reconfigurable SRAM-based cache, non-reconfigurable hybrid cache, and reconfigurable SRAM-based cache, while maintaining the system performance (at most 4% performance overhead).