Selective cache ways: on-demand cache resource allocation
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Direct addressed caches for reduced power consumption
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Fine-grain CAM-tag cache resizing using miss tags
Proceedings of the 2002 international symposium on Low power electronics and design
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Compact thermal modeling for temperature-aware design
Proceedings of the 41st annual Design Automation Conference
Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Low Energy, Highly-Associative Cache Design for Embedded Processors
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Temperature-aware resource allocation and binding in high-level synthesis
Proceedings of the 42nd annual Design Automation Conference
Thermal Management of On-Chip Caches Through Power Density Minimization
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Balancing Resource Utilization to Mitigate Power Density in Processor Pipelines
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
A matrix synthesis approach to thermal placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multiple sleep mode leakage control for cache peripheral circuits in embedded processors
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
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Caches are essential components in embedded processors, taking up a significant fraction of the chip area and power. As a result of the relatively large size and infrequent activity, leakage power of caches is becoming an important problem. There exist a number of power density minimization schemes that distribute the activity evenly among computational entities, thereby lowering the temperature to reduce the leakage power. In this paper, we first present various power density minimization schemes for highly-associative caches in embedded processors via access distribution. It is then suggested that they should be used in conjunction with other power-down techniques to be more effective. We show that conventional power-down techniques for on-chip caches can be suboptimal if thermal effects are ignored, and propose a thermal-aware power-down technique that minimizes power density of the active parts. Simulations based on MediaBench, NetBench, and MiBench applications in a 70nm technology show that the proposed thermal-aware schemes can improve leakage power savings of a conventional power-down technique by 8.5% on average, and up to 23%.