Mitigating Soft Errors in Highly Associative Cache with CAM-based Tag
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Power density minimization for highly-associative caches in embedded processors
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Optimizing CAM-based instruction cache designs for low-power embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
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Many embedded processors use highly associative data caches implemented using a CAM-based tag search. When high-associativity is desirable, CAM designs can offer performance advantages due to fast associative search. However, CAMs are not energy efficient. This paper describes a CAM-based cache design which uses prediction to reduce energy consumption. A last used prediction is shown to achieve an 86% prediction accuracy, on average. A new design integrating such predictor in the CAM tag store is described. A 30% average D-cache energy reduction is demonstrated for the MiBench programs with little additional hardware or impact on processor performance. Even better results can be achieved with another predictor design which increases prediction accuracy. Significant static energy reduction is also possible using this approach for the RAM data store.