Fault-Tolerant Features in the HaL Memory Management Unit
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Energy Efficient Microprocessor Design
Energy Efficient Microprocessor Design
ARM System-on-Chip Architecture
ARM System-on-Chip Architecture
Cache Scrubbing in Microprocessors: Myth or Necessity?
PRDC '04 Proceedings of the 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC'04)
Low Energy, Highly-Associative Cache Design for Embedded Processors
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Cache vulnerability equations for protecting data in embedded processor caches from soft errors
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
SimTag: exploiting tag bits similarity to improve the reliability of the data caches
Proceedings of the Conference on Design, Automation and Test in Europe
An error tolerant CAM with nand match-line organization
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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Content Addressable Memories (CAM) are widely used for the tag portions in highly associative caches. Since data are not explicitly read out of tag array in CAM search, the detection of false misses caused by soft errors for such caches, is difficult. This paper presents a technique to detect the false miss in highly associative cache with CAMbased tag. The technique involves subdividing the tags and providing backup checking for cases the tags are partially matched. An original tag encoding scheme is proposed to reduce the frequency of back-up checking. Modifications to support the technique do not increase the cache access latency. The performance degradation incurred by additional cycles for false miss checking is very low.