An innovative instruction cache for embedded processors

Authors:
Cheol Hong Kim;Sung Woo Chung;Chu Shik Jhon
Affiliations:
Department of Electrical Engineering and Computer Science, Seoul National University, Seoul, Korea;Department of Computer Science, University of Virginia, Charlottesville, Virginia;Department of Electrical Engineering and Computer Science, Seoul National University, Seoul, Korea
Venue:
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Year:
2005

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Abstract

In this paper we present a methodology to enable the design of power efficient instruction cache for embedded processors. The proposed technique, which splits the instruction cache into several small sub-caches, utilizes the locality of applications to reduce dynamic energy consumption in the instruction cache. The proposed cache reduces dynamic energy consumption by accessing only one sub-cache when a request comes into the cache. It also reduces dynamic energy consumption by eliminating the energy consumed in tag matching. In addition, we propose the technique to reduce leakage energy consumption in the proposed cache. We evaluate the design using a simulation infrastructure based on SimpleScalar and CACTI. Simulation results show that the proposed cache reduces dynamic energy by 42% – 59% and reduces leakage energy by 70% – 80%.