Transition density, a stochastic measure of activity in digital circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Cache design trade-offs for power and performance optimization: a case study
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
The filter cache: an energy efficient memory structure
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Way-predicting set-associative cache for high performance and low energy consumption
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Architectural and compiler techniques for energy reduction in high-performance microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
SH3: High Code Density, Low Power
IEEE Micro
Way guard: a segmented counting bloom filter approach to reducing energy for set-associative caches
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Temperature reduction analysis in Sentry Tag cache systems
Proceedings of the 10th workshop on MEmory performance: DEaling with Applications, systems and architecture
MALEC: a multiple access low energy cache
Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper, we focus on low power design at the architecture level and propose a new architecture, called sentry tag, for reducing the on-chip cache power consumption in processors. The many unnecessary activities in the conventional cache-access process motivate our proposal. By pre-comparing the sentry bit of the access address with the sentry tag before starting a normal cache access, we can filter out and eliminate most unnecessary activities. Thus the power consumption can be effectively reduced. Our method is valuable for both a conventional cache with parallel access and a phased cache with serial access. We used SimpleScalar, a trace-driven simulator, to evaluate the performance of our proposed architecture. Compared to a conventional cache, experimental results from SPEC95 benchmarks show that the additional sentry tag can reduce many unnecessary activities (and hence the power consumption), while the hardware overhead is insignificant. For example, an 8-KB, 4-way data cache with two-bit sentry tag can improve the power consumption by 35% compared to a conventional set-associative cache. The maximum power saving achieved using this architecture depends on the cache configuration, which suggests that the proposed sentry tag is a viable choice for data caches with higher associativity.