ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Way-predicting set-associative cache for high performance and low energy consumption
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Selective cache ways: on-demand cache resource allocation
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
SH3: High Code Density, Low Power
IEEE Micro
HotSpot cache: joint temporal and spatial locality exploitation for i-cache energy reduction
Proceedings of the 2004 international symposium on Low power electronics and design
Custom Instruction Filter Cache Synthesis for Low-Power Embedded Systems
RSP '05 Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping
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Cache is an important component of modern processor. On chip instruction cache can comprise one third of CPU power. So both the energy efficiency and performance should be concerned when designing processors. Line buffer cache architecture, which adds a line size buffer between Level 1 cache and IU (integer unit), has the advantage of low energy consumption. But the scheme decreases the performance by about 20%. Prefetch is a useful scheme to improve the performance of processor. In this paper, based on the line buffer cache architecture, the prefetch scheme is introduced in to prefetch the request instructions from Level 1 cache to the line buffer in the hope of improving the processor performance without power consumption increasing significantly. The Leon 2 VHDL model is used as the environment to fulfill the method. The results show that the proposed architecture improves the performance by 12.4% with 4.9% power consumption increasing compared with line buffer cache.