Synthesis of four-phase asynchronous control circuits from pipeline dependency graphs
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Typing Assembly Programs with Explicit Forwarding
TACS '01 Proceedings of the 4th International Symposium on Theoretical Aspects of Computer Software
Memory Faults in Asynchronous Microprocessors
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Journal of Systems Architecture: the EUROMICRO Journal
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Modern, fast microprocessors are deeply pipelined to enhance their performance. Thus they cannot afford to wait for each instruction to complete before starting the next. When inter-instruction dependencies are encoun tered it is essential that data are forwarded from their point of production to where they are needed as rapidly as possible. This has been a problem in asynchronous proces sors because of the lack of synchronisation between the units producing and consuming the data. This paper presents a solution to this problem. The mechanism described allows the depth of speculative execution to be increased, improving memory efficiency by hiding the load latency yet still allowing precise exceptions.