The Manchester Mark I and atlas: a historical perspective
Communications of the ACM - Special issue on computer architecture
Multi-level texture caching for 3D graphics hardware
Proceedings of the 25th annual international symposium on Computer architecture
Retrospective on high-level language computer architecture
25 years of the international symposia on Computer architecture (selected papers)
The University of Manchester MU5 Project
IEEE Annals of the History of Computing
MU6V: a parallel vector processing system
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
The Manchester Mark I and atlas: a historical perspective
Communications of the ACM - Special issue on computer architecture
Distributed simulation of asynchronous hardware: the program driven synchronization protocol
Journal of Parallel and Distributed Computing
Manchester Computer Architectures, 1948-1975
IEEE Annals of the History of Computing
From the other side of the Alantic: how to improve upon the MU5 design
ACM SIGARCH Computer Architecture News
Retrospective on high-level language computer architecture
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
MU6-G. a new design to achieve mainframe performance from a mini-sized computer
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
Reconfigurable Pipeline Systems
ACM '78 Proceedings of the 1978 annual conference
Effective machine descriptors for Ada
SIGPLAN '80 Proceedings of the ACM-SIGPLAN symposium on The ADA programming language
Multiprocessor hardware: An architectural overview
ACM '80 Proceedings of the ACM 1980 annual conference
Effective machine descriptors for Ada
SIGPLAN '80 Proceedings of the ACM-SIGPLAN symposium on Ada programming language
Programming languages and databases
VLDB '78 Proceedings of the fourth international conference on Very Large Data Bases - Volume 4
An Analysis of Instruction-Fetching Strategies in Pipelined Computers
IEEE Transactions on Computers
Adaptable pipeline system with dynamic architecture
AFIPS '81 Proceedings of the May 4-7, 1981, national computer conference
Architectures for supersystems of the '80s
AFIPS '80 Proceedings of the May 19-22, 1980, national computer conference
An Instruction Fetch Unit for a High-Performance Personal Computer
IEEE Transactions on Computers
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Following a brief outline of the background of the MU5 project, the aims and ideas for MU5 are discussed. A description is then given of the instruction set, which includes a number of features conducive to the production of efficient compiled code from high-level language source programs. The design of the processor is then traced from the initial ideas for an associatively addressed “name store” to the final multistage pipeline structure involving a prediction mechanism for instruction prefetching and a function queue for array element accessing. An overall view of the complete MU5 complex is presented together with a brief indication of its performance.