The development of the MU5 computer system
Communications of the ACM - Special issue on computer architecture
An instruction fetch unit for a graph reduction machine
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Design of a high-speed square root multiply and divide unit
IEEE Transactions on Computers
The University of Manchester MU5 Project
IEEE Annals of the History of Computing
MU6V: a parallel vector processing system
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
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MU6-G is a high performance machine useful for general or scientific applications. Its order code and architecture are designed to be sympathetic to the needs of the operating system and to both the compilation and execution of programs written in high level languages and to support a word size suitable for high precision scientific computations. Advanced technology, coupled with simplicity of design, is used to achieve a high and more readily predictable performance. Innovative features include the unique organisation of the virtual memory mapping hardware and the use of a combined operand and instruction buffer-store, accessed using virtual addresses. Fault diagnosis is aided by the inclusion of a microprocessor based diagnostic controller which has read/write access to all bistable devices in the machine and has control of the system clock. The paper includes a description of the various functional units and gives estimates of expected performance.