Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
Solving the state assignment problem for signal transition graphs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A communicating Petri net model for the design of concurrent asynchronous modules
DAC '94 Proceedings of the 31st annual Design Automation Conference
Basic gate implementation of speed-independent circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Externally hazard-free implementations of asynchronous circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A generalized state assignment theory for transformation on signal transition graphs
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Automatic gate-level synthesis of speed-independent circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
SHILPA: a high-level synthesis system for self-timed circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Introduction To Automata Theory, Languages, And Computation
Introduction To Automata Theory, Languages, And Computation
Synthesis of Timed Asynchronous Circuits
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Synthesis of 3D Asynchronous State Machines
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Modeling and optimization of hierarchical synchronous circuits
EDTC '95 Proceedings of the 1995 European conference on Design and Test
SYNTHESIS OF SELF-TIMED VLSI CIRCUITS FROM GRAPH-THEORETIC SPECIFICATIONS
SYNTHESIS OF SELF-TIMED VLSI CIRCUITS FROM GRAPH-THEORETIC SPECIFICATIONS
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