The design of an asynchronous VHDL synthesizer
Proceedings of the conference on Design, automation and test in Europe
An FPGA for Implementing Asynchronous Circuits
IEEE Design & Test
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In this paper, a fully functional prototype of an asynchronous 4-to-4 Address Event Representation (AER) mapper is presented. AER is an event driven communication protocol originally used in VLSI implementations of neural networks to transfer action potentials between neurons. Often, this protocol is used for direct inter-chip communication between neuromorphic chips containing assemblies of neurons. Without an active device between two such chips, the network connections between them are hard-wired in the chip design. More flexibility can be achieved by communicating through an AER mapper: The network can freely be configured and, furthermore, several AER busses can be merged and split to form a complex network structure. We present here an asynchronous AER mapper which offers an easy and versatile solution. The AER mapper receives input from four different AER busses and redirects the input AE to four output AER busses. The control circuitry is implemented on an FPGA and is fully asynchronous, and pipelining is used to maximize throughput. The mapping is performed according to preprogrammed lookup tables, which is stored on external RAM. The mapper can emulate a network of up to 219 direct connections and test results show that the mapper can handle as much as 30× 106 events/second.