Communicating sequential processes
Communicating sequential processes
Acta Informatica
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
The Counterflow Pipeline Processor Architecture
IEEE Design & Test
The Design Problem SCPP-A
Designing Control Logic for Counterflow Pipeline Processor Using Petri Nets
Formal Methods in System Design
Custom Wide Counterflow Pipelines for High-Performance Embedded Applications
IEEE Transactions on Computers
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The Sproull Counterflow Pipeline Processor Architecture has been posed as a common problem in asynchronous design, so as to compare various design methodologies with one another. Using DI-algebra we discuss a path to a decomposition of the problem, which is subsequently shown correct. In the process we discover several design decisions that may have an impact on the performance of such a pipeline. By also introducing two processes that act as the environment of the pipeline, we can restrict the pipeline correctness considerations to one pipeline element and the two environment processes.