Communications of the ACM
Precomputation-based sequential logic optimization for low power
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Investigation into micropipeline latch design styles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Four-phase micropipeline latch control circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI '93 Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration
Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architectural optimization for low-power nonpipelined asynchronous systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
A hybrid design scheme for the synthesis of asynchronous circuits is described which exploits the rapid design time achievable using the Tangram silicon complier (developed by Philips), the high performance of 4-phase micropipelines and the use of synchronous design techniques to increase concurrency and therefore performance. Trade-offs between area, power performance and design time are thus supported. Substantial performance gains and power reduction may be achieved.