Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Using standard asic back-end for qdi asynchronous circuits: dealing with isochronic fork constraint
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Design automation of real-life asynchronous devices and systems
Foundations and Trends in Electronic Design Automation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This thesis presents a design style for implementing communicating sequential processes (CSP) as quasi delay insensitive asynchronous circuits, based on the compilation method of [1]. Although hand compilation can always yield optimal circuits to a good designer, a restricted approach is suggested which can easily implement circuits with some slack between inputs and outputs. These circuits are fast and versatile building blocks for highly pipelined designs. The first chapter presents the implementation approach for individual cells. The second chapter investigates the time behavior of complex pipelined circuits, with the goal of adding slack where necessary and adjusting transistor sizes to optimize the overall throughput.