Four-phase micropipeline latch control circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance Analysis and Optimization of Asynchronous Circuits
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Discrete-Event Control of Stochastic Networks: Multimodularity and Regularity (Lecture Notes in Mathematics)
Performance Evaluation of Asynchronous Concurrent Systems Using Petri Nets
IEEE Transactions on Software Engineering
Accelerating Markovian analysis of asynchronous systems using state compression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a methodology to estimate the latency of the asynchronous pipeline without choices. We propose modeling an asynchronous pipeline with the timed event graph and characterizing its specification via the max-plus algebra. An evolution equation of the event firing epoch can be obtained, which is linear under the max-plus algebraic formalism. In terms of the above-mentioned equation, we can formulate the latency of the pipeline successfully. The case study shows that our method is simple, fast and effective.