Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
Four-phase micropipeline latch control circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Compact, multilayer layout for butterfly fat-tree
Proceedings of the twelfth annual ACM symposium on Parallel algorithms and architectures
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
An Improved Analytical Model for Wormhole Routed Networks with Application to Butterfly Fat-Trees
ICPP '97 Proceedings of the international Conference on Parallel Processing
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The future System-on-Chip (SoC) design will integrate a variety of intellectual properties (IPs). The clocked bus architectures to interconnect the IPs under the deep submicron technology suffer from problems related with the clock distribution, the synchronization of all IPs, the long arbitration delay and the limited bandwidth. These problems can be resolved by adopting new interconnection architecture such as Network-on-Chip (NoC) or the asynchronous design method. In this paper, a design methodology for an asynchronous switch based on butterfly fat-tree topology is proposed. The wormhole switching technique is adopted to reduce the latency and the buffer size. The source-based routing mechanism and the output buffering strategy are used to reduce the switch design cost and increase the performance.