Performance of iterative computation in self-timed rings
Journal of VLSI Signal Processing Systems - Special issue: asynchronous circuit design for VLSI signal processing
Four-phase micropipeline latch control circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Asynchronous Circuits: An Increasingly Practical Design Solution
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Latency and throughput tradeoffs in self-timed speed-independent pipelines and rings
Latency and throughput tradeoffs in self-timed speed-independent pipelines and rings
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
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Asynchronous logic is a hot topic due to its interesting features of power saving, low noise and robustness to parameters variations. However, its performance analysis is relatively complex. In fact, the handshaking protocol strongly influences the performance of the pipelined architectures. This paper introduces verified Standard-Logic schematics for QDI asynchronous latches and analyzes their characteristics. Buffering capacity and protocol gain are defined and analyzed. Based on this analysis, reduced performance equations are first introduced. By means of the dependency graphs, a new formal method is then proposed to analyze the performance of asynchronous linear-pipeline. This methodology is used to derive general equations for each latch type. Contrarily to previously proposed methods, this method can be applied to any asynchronous linear-pipeline without restrictions on its functional block delays. Therefore, the contributions of this paper enable the designers to understand the benefits brought by the different asynchronous latches, to compare them and make the right choice according to their design constrains....