The happy marriage of architecture and application in next-generation reconfigurable systems
Proceedings of the 1st conference on Computing frontiers
The CBP Parameter: A Module Characterization Approach for DSP Software Optimization
Journal of VLSI Signal Processing Systems
Retargeting Sequential Image-Processing Programs for Data Parallel Execution
IEEE Transactions on Software Engineering
Modeling of Block-Based DSP Systems
Journal of VLSI Signal Processing Systems
Multidimensional DSP Core Synthesis for FPGA
Journal of VLSI Signal Processing Systems
Analysis of Dataflow Programs with Interval-limited Data-rates
Journal of VLSI Signal Processing Systems
Software synthesis from the dataflow interchange format
SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
Rapid implementation and optimisation of DSP systems on FPGA-centric heterogeneous platforms
Journal of Systems Architecture: the EUROMICRO Journal
Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis
Journal of Signal Processing Systems
OpenDF: a dataflow toolset for reconfigurable hardware and multicore systems
ACM SIGARCH Computer Architecture News
Multidimensional Systems and Signal Processing
SoC Memory Hierarchy Derivation from Dataflow Graphs
Journal of Signal Processing Systems
Journal of Systems Architecture: the EUROMICRO Journal
Rapid implementation and optimisation of DSP systems on SoPC heterogeneous platforms
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
DART--a High Level Software-Defined Radio Platform Model for Developing the Run-Time Controller
Journal of Signal Processing Systems
A SWP specification for sequential image processing algorithms
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
Development and Evaluation of Distributed Simulation of Embedded Systems Using Ptolemy and HLA
DS-RT '13 Proceedings of the 2013 IEEE/ACM 17th International Symposium on Distributed Simulation and Real Time Applications
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Signal flow graphs with dataflow semantics have been used in signal processing system simulation, algorithm development, and real-time system design. Dataflow semantics implicitly expose function parallelism by imposing only a partial ordering constraint on the execution of functions. One particular form of dataflow called synchronous dataflow (SDF) has been quite popular in programming environments for digital signal processing (DSP) since it has strong formal properties and is ideally suited for expressing multirate DSP algorithms. However, SDF and other dataflow models use first-in first-out (FIFO) queues on the communication channels and are thus ideally suited only for one-dimensional (1-D) signal processing algorithms. While multidimensional systems can also be expressed by collapsing arrays into 1-D streams, such modeling is often awkward and can obscure potential data parallelism that might be present. SDF can be generalized to multiple dimensions; this model is called multidimensional synchronous dataflow (MDSDF). This paper presents MDSDF and shows how MDSDF can be efficiently used to model a variety of multidimensional DSP systems, as well as other types of systems that are not modeled elegantly in SDF. However, MDSDF generalizes the FIFO queues used in SDF to arrays and, thus, is capable only of expressing systems sampled on rectangular lattices. This paper also presents a generalization of MDSDF that is capable of handling arbitrary sampling lattices and lattice-changing operations such as nonrectangular decimation and interpolation. An example of a practical system is given to show the usefulness of this model. The key challenge in generalizing the MDSDF model is preserving static schedulability, which eliminates the overhead associated with dynamic scheduling, and preserving a model where data parallelism, as well as functional parallelism, is fully explicit