Rate-optimal schedule for multi-rate DSP computations
Journal of VLSI Signal Processing Systems - Special issue on application-specific array processors
Efficient algorithms for optimum cycle mean and optimum cost to time ratio problems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Software Synthesis from Dataflow Graphs
Software Synthesis from Dataflow Graphs
Embedded Multiprocessors: Scheduling and Synchronization
Embedded Multiprocessors: Scheduling and Synchronization
Predictable embedding of large data structures in multiprocessor networks-on-chip
DSD '05 Proceedings of the 8th Euromicro Conference on Digital System Design
ACSD '06 Proceedings of the Sixth International Conference on Application of Concurrency to System Design
Throughput Analysis of Synchronous Data Flow Graphs
ACSD '06 Proceedings of the Sixth International Conference on Application of Concurrency to System Design
Efficient computation of buffer capacities for cyclo-static dataflow graphs
Proceedings of the 44th annual Design Automation Conference
Latency Minimization for Synchronous Data Flow Graphs
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Execution-time Prediction for Dynamic Streaming Applications with Task-level Parallelism
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Throughput-Buffering Trade-Off Exploration for Cyclo-Static and Synchronous Dataflow Graphs
IEEE Transactions on Computers
Synchronous dataflow scenarios
ACM Transactions on Embedded Computing Systems (TECS)
Worst-case performance analysis of synchronous dataflow scenarios
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Synchronous dataflow scenarios
ACM Transactions on Embedded Computing Systems (TECS)
FORMLESS: scalable utilization of embedded manycores in streaming applications
Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Systems
A new data flow analysis model for TDM
Proceedings of the tenth ACM international conference on Embedded software
Compositionality in synchronous data flow: Modular code generation from hierarchical SDF graphs
ACM Transactions on Embedded Computing Systems (TECS)
Analysis of multi-domain scenarios for optimized dynamic power management strategies
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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The Synchronous Dataflow (SDF) model of computation is popular for modelling the timing behaviour of real-time embedded hardware and software systems and applications. It is an essential ingredient of several automated design-flows and design-space exploration tools. The model can be analysed for throughput and latency properties. Although the SDF model is fairly simple, the analysis algorithms are often of high complexity and the models that need to be analysed may be fairly large. This paper introduces two graph transformations for reducing large SDF graphs into simpler, smaller ones that can be analysed more efficiently and give a conservative and often tight estimation of the timing of the original model and hence of the hard real-time system. We can make SDF based methods more efficient and prove that analyses that were done manually in an ad-hoc fashion in the past, can be done automatically and with guaranteed correctness. Additionally we introduce a novel conversion from SDF to Homogeneous SDF, a step applied in many analysis methods for SDF, which yields an up to 250X improvement on the number of actors, thus mitigating the problems with the size explosion observed in the traditional conversion.