Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
Discrete flow networks: bottleneck analysis and fluid approximations
Mathematics of Operations Research
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Synthesis of Embedded Software from Synchronous Dataflow Specifications
Journal of VLSI Signal Processing Systems
An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Minimising buffer requirements of synchronous dataflow graphs with model checking
Proceedings of the 42nd annual Design Automation Conference
A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels
IEEE Transactions on Computers
Proceedings of the 43rd annual Design Automation Conference
ACSD '06 Proceedings of the Sixth International Conference on Application of Concurrency to System Design
Throughput Analysis of Synchronous Data Flow Graphs
ACSD '06 Proceedings of the Sixth International Conference on Application of Concurrency to System Design
Efficient symbolic multi-objective design space exploration
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Throughput-Buffering Trade-Off Exploration for Cyclo-Static and Synchronous Dataflow Graphs
IEEE Transactions on Computers
SPARTAN: A software tool for Parallelization Bottleneck Analysis
IWMSE '09 Proceedings of the 2009 ICSE Workshop on Multicore Software Engineering
System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Towards performance analysis of SDFGs mapped to shared-bus architectures using model-checking
Proceedings of the Conference on Design, Automation and Test in Europe
Playing games with scenario- and resource-aware SDF graphs through policy iteration
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Design of streaming applications on MPSoCs using abstract clocks
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Modeling static-order schedules in synchronous dataflow graphs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Journal of Systems Architecture: the EUROMICRO Journal
| Hi-index | 0.00 |
Media processing systems often have limited resources and strict performance requirements. An implementation must meet those design constraints while minimizing resource usage and energy consumption. Design-space exploration techniques help system designers to pinpoint bottlenecks in a system for a given configuration. The trade-offs between performance and resources in the design space can guide designers to tailor and tune the system. Many applications in those systems are computationally intensive and can be modeled by a synchronous dataflow graph. We present a bottleneck-analysis-driven technique to explore the design space of those systems automatically and incrementally. The feasibility and efficiency of the technique is demonstrated with experiments on a set of realistic application models ranging from multimedia to digital printing.