Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs

Authors:
Jun Zhu;Ingo Sander;Axel Jantsch
Affiliations:
Royal Institute of Technology, Stockholm, Sweden;Royal Institute of Technology, Stockholm, Sweden;Royal Institute of Technology, Stockholm, Sweden
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2010

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Abstract

We present a Pareto efficient design method for multi-dimensional optimization of run-time reconfigurable streaming applications on CPU/FPGA platforms, which automatically allocates applications with optimized buffer requirement and software/hardware implementation cost. At the same time, application performance is guaranteed with sustainable throughput during run-time reconfigurations. As the main contribution, we formulate the constraint based application allocation, scheduling, and reconfiguration analysis, and propose a design Pareto-point calculation flow. A public domain solver - Gecode is used in solutions finding. The capability of our method has been exemplified by two cases studies on applications from media and communication domains.