Hardware/software partitioning and pipelined scheduling on runtime reconfigurable FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs
Proceedings of the Conference on Design, Automation and Test in Europe
OveRSoC: a framework for the exploration of RTOS for RSoC platforms
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
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FPGAs are often used together with a CPU as hardware accelerators. A runtime reconfigurable FPGA allows part of the FPGA area to be reconfigured while the remainder continues to operate without interruption, so that hardware tasks can be placed and removed dynamically at runtime. In this paper, we formulate and solve the problem of optimal hardware/software partitioning and static task scheduling for a hybrid FPGA/CPU device, with the optimization objective of minimizing the total schedule length, in the framework of Satisfiability Modulo Theories (SMT) with Linear Integer Arithmetic.