IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Creating 35 mm Camera Active Pixel Sensors
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Self-Configuration of a Large Area Integrated Multiprocessor System for Video Applications
DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Task-level timing models for guaranteed performance in multiprocessor networks-on-chip
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing
Journal of VLSI Signal Processing Systems
| Hi-index | 0.00 |
This 16.89-cm2 multiprocessor system performs coding of high-resolution video streams in real time. Redundancy and self-reconfiguration techniques ensure high reliability with a suitable yield.