Predictable Embedding of Large Data Structures in Multiprocessor Networks-on-Chip

Authors:
Sander Stuijk;Twan Basten;Bart Mesman;Marc Geilen
Affiliations:
Eindhoven University of Technology, The Netherlands;Eindhoven University of Technology, The Netherlands;Eindhoven University of Technology, The Netherlands/ Philips Research Laboratories, The Netherlands;Eindhoven University of Technology, The Netherlands
Venue:
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Year:
2005

Citing 3
Cited 0

Parallel Computer Architecture: A Hardware/Software Approach

Parallel Computer Architecture: A Hardware/Software Approach
Scheduling dynamic dataflow graphs with bounded memory using the token flow model

Scheduling dynamic dataflow graphs with bounded memory using the token flow model
Task-level timing models for guaranteed performance in multiprocessor networks-on-chip

Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems

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Abstract

This extended abstract presents models to derive timing and resource usage numbers for an application when distant, shared memories are used in an important class of future embedded platforms, namely network-on-chip-based multiprocessors.