NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Design tradeoffs for tiled CMP on-chip networks
Proceedings of the 20th annual international conference on Supercomputing
Flattened butterfly: a cost-efficient topology for high-radix networks
Proceedings of the 34th annual international symposium on Computer architecture
Express virtual channels: towards the ideal interconnection fabric
Proceedings of the 34th annual international symposium on Computer architecture
Three-Dimensional Layout of On-Chip Tree-Based Networks
ISPAN '08 Proceedings of the The International Symposium on Parallel Architectures, Algorithms, and Networks
Introduction to the Special Section on Networks-on-Chip
IEEE Transactions on Computers
Dynamic load balancing through real-time transport feedback control for VoIP QoS
International Journal of Computer Applications in Technology
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multi-state reliability and message time delay in wireless sensor networks
International Journal of Wireless and Mobile Computing
An improved ant colony optimisation and its application on multicast routing problem
International Journal of Wireless and Mobile Computing
International Journal of Wireless and Mobile Computing
A multi-level design methodology of multistage interconnection network for MPSOCs
International Journal of Computer Applications in Technology
International Journal of Computer Applications in Technology
Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
Researches on network-on-chip NoC topology are ongoing in 2-dimensional or 3-dimensional space. However, for the current topology in 2-dimensional space, the long communications delay is the biggest problem; while, for the topology in 3-dimensional space, high complexity of the routing algorithm and difficulty of physical implementation cannot be solved. Therefore, we propose a novel kind of topology named half-mesh. The half-mesh introduces binary search, and based on mesh, processing unit in system central as an original point, along the X, Y direction, respectively, increases the head nodes and intermediate nodes. Therefore, it shortens the path length between nodes, and ensures the diversity of paths. As to half-mesh structure, we put forward to half-test-feedback-XY HTF-XY. According to the area where the destination node lies, we adopt a different routing strategy to achieve minimum latency between routers. Theoretical analysis and experimental results show that half-mesh structure, compared with the mesh and torus, has the advantage of short routing path, throughput, and load balancing.