Early stage power management for 3D FPGAs considering hierarchical routing resources

Authors:
Krishna Chaitanya Nunna;Farhad Mehdipour;Kazuaki Murakami
Affiliations:
Kyushu University, Fukuoka, Japan;Kyushu University, Fukuoka, Japan;Kyushu University, Fukuoka, Japan
Venue:
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Year:
2013

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Abstract

Designing for low power consumption demands power-efficient devices and good design practices to leverage the architectural features without compromising performance. Power estimation at an early stage of electronic design automation (EDA) flow is essential in order to handle the design issues much earlier. In this paper, we are proposing a methodology for evaluating the power in three-dimensional field-programmable gate arrays (3D FPGAs) at an early stage of the design cycle namely at the partitioning step and making it a power-aware stage. As a part of the work, we also estimate the routing resources needed for the power evaluation. Our estimated power values are compared against the values obtained from a 3D place and route tool, TPR along with the added power calculations, which is demonstrating acceptable accuracy. Our results show that there is a scope for achieving desired distribution of power among the layers well before the placement with reasonable deviation in estimation and proves that our methodology is providing opportunity for power management at earlier stages of the design flow.