Easily Testable Iterative Logic Arrays
IEEE Transactions on Computers
Analysis and Testing for Error Tolerant Motion Estimation
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
An efficient VLSI architecture for H.264 variable block size motion estimation
IEEE Transactions on Consumer Electronics
An efficient hardware implementation for motion estimation of AVC standard
IEEE Transactions on Consumer Electronics
A novel all-binary motion estimation (ABME) with optimized hardware architectures
IEEE Transactions on Circuits and Systems for Video Technology
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In this paper, testable design techniques for variable block size motion estimators used in H. 264/AVC are proposed. The whole motion estimator can be viewed as an iterative logic array (ILA) consisting of basic cells (modules). Design-for-testability techniques are applied for the cell (module) function such that the M-testability conditions proposed in previous works can be met for the motion estimation array. The goal of the DFT techniques is to make the cell (module) function bijective. The M-testability conditions guarantee 100% single-cell (module)-fault testability with a minimum number of test patterns. The hardware overhead and the number of test patterns are 4.22% and 128, respectively.