Estimating Error Rate in Defective Logic Using Signature Analysis
IEEE Transactions on Computers
Proceedings of the conference on Design, automation and test in Europe
Error Rate Estimation for Defective Circuits via Ones Counting
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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In the near future all die implementing high performancecircuitry will contain hundreds of thousands of defects.Most companies will attempt to achieve useful levels offunctionally good die using classical and enhanced faulttolerant and defect tolerant techniques. We advocate anew notion for yield enhancement called error tolerancethat includes marketing chips that occasionally outputerrors. The quantity and quality of errors produced by achip can be characterized several ways, such as byaccuracy, error rate, and accumulation (retention). Thispaper focuses on test techniques for estimating errorrate.