A Fast Threshold Test Generation Algorithm Based on 5-Valued Logic

  • Authors:

  • Tomoo Inoue;Nobukazu Izumi;Yuki Yoshikawa;Hideyuki Ichihara

  • Affiliations:

  • -;-;-;-

  • Venue:
  • DELTA '10 Proceedings of the 2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications
  • Year:
  • 2010

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Abstract

Threshold testing, which is a VLSI testing method based on the acceptability of faults, is effective in yield enhancement of VLSIs and in selectively hardening VLSI systems. A test generation algorithm for generating test patterns for unacceptable faults has been proposed, which is based on the 16-valued logic system. In this paper, we propose a fast test generation algorithm based on the 5-valued logic system. Experimental results show that our proposed algorithm can generate test patterns for unacceptable faults with small computational time, compared with that based on the 16-valued logic system.