Threshold testing: improving yield for nanoscale VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hardware that produces bounded rather than exact results
Proceedings of the 47th Design Automation Conference
Error Rate Estimation for Defective Circuits via Ones Counting
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.03 |
In the recent years, yields for digital VLSI chips have been declining and the decline is expected to accelerate. We have recently proposed a new testing approach called threshold testing, with the goal of providing acceptable yields in future processes for a wide range of high performance digital applications, including audio, speech, video, graphics, visualization, games, and wireless communication. The motivation of this paper is to answer the following question: Do threshold tests generated for stuck-at faults provide as high a threshold coverage for realistic faults as the classical coverage for realistic faults provided by classical stuck-at test sets? Using a combination of analysis and experiments, we show that the stuck-at fault model is indeed a suitable model for threshold testing. This opens the way for developing low cost tools for threshold testing that will provide high threshold coverage for realistic faults, and hence help provide higher yields in future processes at low costs. We also present a threshold automatic test pattern generator (ATPG) for bridging faults.