Error Rate Estimation for Defective Circuits via Ones Counting
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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As feature size reduces to nanoscale, it becomes increasingly more expensive and difficult to reach a desired level of yield. Error-tolerance, which advocates the use of defective chips in systems as long as acceptable performance is obtained, has been proposed as a new way to enhance effective yield. As distinct from classical test, test for error-tolerance focuses on quantifying the error-metrics for acceptability of defective chips. Error-rate is one such metric. To estimate error-rate, a signature analysis based method and a ones counting based method have been previously proposed. Unfortunately, the ones counting based error-rate estimation method previously reported must be applied to each output of a multi-output circuit one line at a time. In this paper, we present a method for applying this ones counting technique to a multi-output circuit, i.e., to a pattern rather than a bit. We divide this problem into four parts and present the solution to three or them; the fourth is still an open problem.