PLATYPUS: a PLA test pattern generation tool
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Introduction to VLSI Systems
The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis
IEEE Transactions on Computers
A defect-tolerant and fully testable PLA
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Fully testable PLA design with minimal extra input
EURO-DAC '90 Proceedings of the conference on European design automation
A BIST design of structured arrays with fault-tolerant layout
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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A method for designing easily testable PLA's with low overhead is presented. The method is based on a reduction of product lines and the addition of a small number of inputs. The required additional hardware is calculated using a statistical cooling algorithm. The presented design-for-testability method guarantees a 100 percent fault coverage with respect to multiple stuck-at faults and multiple missing/extra crosspoint faults.