Thread-associative memory for multicore and multithreaded computing

Authors:
Shuo Wang;Lei Wang
Affiliations:
University of Connecticut, Storrs, CT;University of Connecticut, Storrs, CT
Venue:
Proceedings of the 2006 international symposium on Low power electronics and design
Year:
2006

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Abstract

Presented in this paper is the thread-associative memory microarchitecture for multicore and multithreaded processor design. Memory contention among concurrent threads in chip multithreaded processing has become a limiting factor for performance improvement. The proposed thread-associative memory addresses this challenge by incorporating thread-specific information explicitly into on-chip memory hardware. The proposed technique can be utilized at different levels of memory hierarchy. Furthermore, it is not just a technique for performance enhancement but also a solution for energy efficiency. Trace-driven simulations on a 32KB L1 data cache demonstrate 36.6% maximum performance improvement and up to 15.1% total energy reduction, with 20.3% dynamic energy reduction and 9.9% leakage energy reduction.