Circuit optimization techniques to mitigate the effects of soft errors in combinational logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A low-cost, systematic methodology for soft error robustness of logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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It is expected that the soft error rate (SER) of combinational logic will increase significantly. Previous solutions to mitigate soft errors in combinational logic suffer from delay penalty or area/power overhead. In this paper, we proposed an output remapping technique to reduce SER of critical paths. Experimental results show up to about 20X increase in Qcritical. So the SER is reduced significantly. This method does not introduce any delay penalty. The area/power overhead is limited as well. The output remapping method is based on our novel glitch width model. The analysis shows that output remapping technique works well along with technology scaling.